A) Field of the Invention
This invention relates to a thin film transistor (TFT) substrate and a liquid crystal display and especially to those having additional or subsidiary storage capacitors.
B) Description of the Related Art
Recently, a liquid crystal display is widely used for an information device, etc., and lower cost and higher resolution are sought. Most of thin film transistor substrates have additional or subsidiary storage capacitors for storing information for pixel electrodes at respective pixels. The additional storage capacitor is generally formed with an opaque body, and therefore causes a reduction in an effective pixel area. Miniaturization of the additional storage capacitor that occupies a comparatively large region is demanded. Also, in a manufacturing process of the additional storage capacitor, interlayer short-circuit etc. causes defections. Decreasing the defections is expected.
FIGS. 5A to 5D show examples of configurations of thin film transistor substrates according to the prior art.
FIG. 5A is a plan view showing a thin film transistor substrate by the conventional technology. FIG. 5B is a cross sectional view showing a part of a thin film transistor along the line VB-VB in FIG. 5A, and FIG. 5C is a cross sectional view showing an additional storage capacitor part along the line VC-VC in FIG. 5A.
A gate bus line 2t and an additional storage capacitor bus line 2c are formed by patterning a metallic layer on a substrate 1 having an insulating surface such as a glass substrate or the like. The bus lines 2t and 2c are electrically isolated from each other. An insulating layer 3 such as a silicon nitride or the like is formed on the entire surface of the substrate 1 so as to cover the bus lines 2t and 2c. The insulating layer 3 forms a gate insulating film 3t in the thin film transistor region and a dielectric film of a capacitor 3c in the additional storage capacitor region.
A high resistivity amorphous silicon layer that can form a thin film transistor channel (11t, 11c) is deposited on an insulating layer 3, and thereon a silicon nitride layer having a function of an etching stopper is deposited. The silicon nitride layer is patterned to remain as a channel protection layer 12t only in the thin film transistor channel region. An n+-type amorphous silicon layer that is highly doped with n-type impurity is deposited on the high resistivity amorphous silicon layer so as to cover the channel protection layer 12t. The amorphous silicon layer and the silicon nitride layer are deposited by, for example, chemical vapor deposition (CVD).
A Ti layer 4a, an Al layer 4b and a Ti layer 4c are laminated on an amorphous silicon layer, for example, by sputtering. A resist pattern is formed on the Ti layer 4c, and the Ti layer 4c, the Al layer 4b, the Ti layer 4a, the n+ type amorphous silicon layer and the high resistivity amorphous silicon layer are patterned into, respectively, 13t/13c and 11t/11c. The channel protection layer 12t is formed on the channel region; therefore, the etching on the channel region is stopped at the channel protection layer 12t, and the high resistivity amorphous silicon layer underneath is not etched.
As described above, source/drain electrodes and an upper electrode of the capacitor are formed in the thin film transistor region and the additional storage capacitor region.
Covering the Ti layer 4c, an insulating protection layer 14, for example, of silicon nitride, is deposited on an insulating layer 3 by CVD or the like. Contact apertures 8t and 8c are formed on a source region of the thin film transistor and an upper electrode of a connecting region of the additional storage capacitor. In this etching process, for example, if a pinhole exists on the Ti layer 4c, the Al layer 4b and the Ti layer 4a, the etching reaches the layer underneath.
When a pinhole exists in a metallic lamination at the bottom of a connection hole 8c in FIG. 5C, the etching reaches the amorphous silicon layers 13c, 11c, and the lower insulating layer 3c, and may reach the lower electrode 2c. 
Then, an indium-tin oxide (ITO) layer 5 is deposited on the insulating protection layer 14 covering the connection hole, and patterned to form a pixel electrode. If the lower electrode 2c is exposed by a pinhole, a pixel electrode 5 short-circuits the lower and the upper electrodes, and a capacitor loses its function.
FIG. 5D shows an example of a structure having a contact of the upper electrode to the pixel electrode outside the lower electrode to prevent the short circuit. Because the contact of the upper electrode is formed outside the lower electrode, the short circuit can be prevented even if a pinhole exists. However, the lower and the upper electrodes are both opaque layers so that an effective area of the pixel electrode decreases in such degree that the upper electrode extends outside the lower electrode.
In the thin film transistor substrate having an additional storage capacitor, preventing the short circuit between the electrodes of the additional storage capacitor and obtaining a valid pixel area as large as possible were difficult.